1. Field of the Invention
The invention generally relates to memory testing.
2. Description of the Related Art
One technique to test dynamic random access memory (DRAM) entails writing predetermined data to the memory, reading data from the memory, and identifying whether the read data matches the written data to help verify whether the memory functions properly. Different data topologies may be written to the memory to help detect various defects or faults (e.g., solids ‘1111’, stripes ‘1010’, etc.). Selection of appropriate test data topologies may depend, for example, on the defect(s) and/or fault(s) to be detected and the architecture of the memory.
To write a desired test data topology into memory, a tester issues WRITE commands to the memory, requiring the memory to perform a series of steps, for each row of memory cells to be tested. For example, the memory may perform a series of steps to activate a row of memory cells, sequentially address columns of memory cells to write data in accordance with the test data topology to memory cells common to the activated row and each addressed column, and deactivate the activated row to allow another row of memory cells to be accessed.
For various reasons (e.g., geometry, yield, and speed optimizations) memory devices often have physical memory topologies employing “scrambling” techniques where logically adjacent addresses and/or data are not physically adjacent. As a result, to achieve a desired effect of testing with a particular data topology, this scrambling must be taken into account, for example, by transforming (or mapping) sequential addresses into non-sequential addresses, as dictated by the particular scrambling circuitry used on the device, at the tester.
Unfortunately, compensating for scrambling in this manner complicates the development of test programs. Therefore, what is needed is a method and apparatus that facilitate the testing of memory devices utilizing scrambling.